Multiplexer MCQ Quiz - Objective Question with Answer for Multiplexer - Download Free PDF

Explanation:

3-bit Gray Counter Controlled Multiplexer

Definition: A 3-bit Gray counter is a type of binary counter in which two successive values differ in only one bit. This counter is used to control the output of a multiplexer, which selects one of several input signals and forwards the selected input to a single output line.

Working Principle: In the given scenario, the 3-bit Gray counter is used to control the multiplexer’s output. The counter starts from an initial state of 000 and goes through a sequence of states where only one bit changes at a time. The output of the multiplexer is pulled high when it is not enabled.

The Gray code sequence for a 3-bit counter is as follows:

• 000
• 001
• 011
• 010
• 110
• 111
• 101
• 100

Sequence Analysis:

With the initial state of the counter being 000, the multiplexer will follow the Gray code sequence mentioned above. The multiplexer is enabled only for certain states, and the output is high (1) when it is not enabled. Let’s analyze the sequence step-by-step:

1. 000: Multiplexer selects I0.
2. 001: Multiplexer is not enabled, output is 1.
3. 011: Multiplexer is not enabled, output is 1.
4. 010: Multiplexer selects I1.
5. 110: Multiplexer selects I3.
6. 111: Multiplexer is not enabled, output is 1.
7. 101: Multiplexer is not enabled, output is 1.
8. 100: Multiplexer selects I2.

Based on this analysis, the output sequence of the circuit is:

I0, 1, 1, I1, I3, 1, 1, I2

Correct Option Analysis:

The correct option is:

Option 1: I0, 1, 1, I1, I3, 1, 1, I2

This option correctly describes the output sequence of the multiplexer controlled by the 3-bit Gray counter

Calculation:

The number of input lines in a available multiplexer is 2ⁿ.

The number of input lines in a desired multiplexer is 2^N.

The number of individual multiplexer required to construct the desired multiplexers circuit is equal to the ratio of The number of input lines in a desired multiplexer to the number of input lines in a available multiplexer. 

i.e., \(\frac{2^N}{2^n}\)

= \(2^{N-n}\)

Concept:

Multiplexer:

The multiplexer is a combinational logic circuit designed to switch one of several input lines to a single common output line.

• The multiplexer or “MUX” is a combinational logic circuit designed to switch one of several input lines through a single common output line by the application of a control signal.
• Multiplexers operate like very acting multiple position rotary switches connecting or controlling multiple input lines called “channels” one at a time to the output.
• Multiplexers are used to convert parallel to serial data.

Additional Information 

De-multiplexer:

• The demultiplexer is a combinational logic circuit designed to switch one common input line to one of several separate output lines.
• The data distributor, known as a Demultiplexer or “Demux”, works in just the opposite way to that of the Multiplexer.
• The demultiplexer takes one single input data line and then switches it to any one of a number of individual output lines one at a time.

The block diagram is as shown:

Application:

The demultiplexer converts a serial data signal at the input to parallel data at its output lines as shown below.

The function of the Demultiplexer is to switch one common data input line to any one of the 4 output data lines A to D.

Concept:

For a 2 × 1 MUX as shown above, the output function F is expressed as:

F = S̅1 I0 + S1I1

i.e. when S1 = 0, I0 is transmitted to the output.

And when S1 = 1, I1 is transmitted to the output.

Calculation:

For the given figure 

\(Y=\bar Q.0+Q.P\)

Y = PQ

The Correct Answer is option 1.

Concept:

Multiplexers:

• Multiplexers are combinational circuits designed to select one of multiple data inputs and produce a single output
• They're commonly used in communication transmissions
• A multiplexer is Many to one data selector
• A multiplexer selects one of the many data available at its input depending on the bits on the select line
• For 2n inputs, there are n select lines that determine, which input is to be connected to the output.

Concept:

In a 4 × 1 MUX

Truth-Table

Y = Output = S̅₁ S̅₀ I₀ + S̅₁ S₀ I₁ + S₁ S̅₀ I₂ + S₁ S₀ I₃

MUX contains AND gate followed by OR gate

Calculation:

By re-drawing circuit diagram

∴ I₀ = 0, I₁ = 1, I₂ = 1, I₃ = 0 & (P = S₁, Q = S₀)

Now output of 4 × 1 MUX is

Y = F = (P̅ Q̅) 0 + (P̅ Q)1 + (P Q̅) 1 + (P Q)0

∴ F = P Q̅ + P̅ Q = P ⊕ Q

∴ F = XOR (P, Q) 

Concept: 

For a 2 × 1 MUX is shown above, the output function F is expressed as:

F = S̅₁ I₀ + S₁I₁

i.e. when S₁ = 0, I₀ is transmitted to the output.

And when S₁ = 1, I₁ is transmitted to the output.

Analysis:

The given circuit is redrawn as:

F₁ = S̅₁ w + S₁ w̅

F₁ = S₁ ⊕ w

Now, the required function f will be:

F₂ = F = S̅₂F₁ + S₂F̅₁

F = S₂ ⊕ F₁

F = S₂ ⊕ S₁ ⊕ w

Multiplexer:

• A multiplexer is Many to one data selector.
• A multiplexer selects one of the many data available at its input depending on the bits on the select line.
• For 2m inputs, there are m select lines that determine, which input is to be connected to the output, i.e.

          Number of control lines = log2(number of input lines)

So, m control lines can create 2m combinations

Calculation:

Given:

Control lines in a multiplexer is 5.

5 control lines can create 25 = 32 combinations

Hence, the size of Mux is 32 ∶ 1

Concept:

In a 4 × 1 MUX

Truth-Table

Y = Output = S̅1 S̅0 I0 + S̅1 S0 I1 + S1 S̅0 I2 + S1 S0 I3

MUX contains AND gate followed by OR gate

Calculation:

By re-drawing the circuit diagram

∴ I0 = 1, I1 = 0, I2 = 0, I3 = 0 & (x= S2, y = S1)

Now output of 4 × 1 MUX is

Y = F = S̅₁ S̅₂ I0 + S̅1 S₂ I1 + S1 S̅₂ I2 + S1 S₂ I3

F = x̅ y̅ 1 + x̅ y 0 + x y̅ 0 + x y 0

∴ F =  x̅ y̅  = \(\rm{\overline{x + y}}\)

Concept: 

For a 2 × 1 MUX is shown above, the output function F is expressed as:

F = S̅1 I0 + S1I1

i.e. when S1 = 0, I0 is transmitted to the output.

And when S1 = 1, I1 is transmitted to the output.

Application:

For the given MUX, the output expression will be:

Y = A̅ B + AB̅ 

Y = A XOR B

Concept:

Half Adder:

Half Adder is an arithmetic combinational circuit that adds two numbers and produces a sum bit (s) and carry bit (C) as the output.

If A and B are the input bits, then sum bit (s) is the XOR of A and B and the carry bit (C) will be the AND of A and B.

Truth table of Half Adder is given below

S = A ⊕ B

C = A ⋅ B

The half adder can odd only two input bits (A and B) and has nothing to do with the carry if there is any input.

So if the input to a half adder have a carry, then it will be neglected it and add only the A and B bits, which means the binary addition process is not complete and that’s why it is called a half adder.

Multiplexer (MUX):

Multiplexer (MUX) is a combinational logic circuit designed to switch one of several input lives through a single common output line by application of control signal.

Output expression of 4:1 Mux is

Q = a̅ b̅ A + a̅ b B + a b̅ C + a b D

Calculation:

Given:

A = 1 ; B = 1 ; S₀ = lower bit

S₁ = upper bit

We know output of half Adder

S = A ⊕ B

C = A ⋅ B

∴ S = 1 ⊕ 1 = 0

C = 1.1 = 1

EXOR

AND

Now, output of MUX is

Y = S̅₁ S̅₀ I₀ + S̅₁ S₀ I₁ + S₁ S̅₀ I₂ + S₁ S₀ I₃

Where

S₁ = S = 0

S₀ = C = 1

∴ Y = 0̅.1̅ . I₀ + 0̅ . 1 . I₁ + 0.1̅.I₂ + 0.1.I₃

Y = 1.0.I₀ + 1.1.I₁ + 0.0.I₂ + 0.1.I₃

Y = 0 + I₁ + 0 + 0

Y = I₁

NOTE:

If someone took ‘S₀’ as upper bit and ‘S₁’ as lower bit, it would display wrong answer. As:

Y = 1̅.0̅.I₀ + 1̅.0̅.I₁ + 1.0̅.I₂ + 1.0.I₃

Y = 0.1.I₀ + 0.0.I₁ + 1.1.I₂ + 1.0.I₃

Y = 0 + 0 + I₂ + 0

Y = I₂

Calculation:

For the given MUX, the output is given by,

\(Z=\bar{X}\bar{Y}{{I}_{0}}+\bar{X}Y{{I}_{1}}+X\bar{Y}{{I}_{2}}+XY{{I}_{3}}\)

Given I₀ = X, I₁ = Y, I₂ = X and I₃ = 0

Now, \(Z=\bar{X}\bar{Y}\left( X \right)+\bar{X}Y\left( Y \right)+X\bar{Y}\left( X \right)+XY\left( 0 \right)\)

= 0 + X̅Y + XY̅ + 0

= X̅Y + XY̅

= X ⊕ Y (X-OR gate)

The output of the first multiplexer will be:

A = U̅V̅0 + U̅V.1 + UV̅.1 + UV.0

A = (U̅V + UV̅)   ---(1)

Now, the output of second multiplexer will be:

F = A.(W̅ X̅) + A(W̅X) + 0.(WX̅) + 0.(WX)

F = AW̅ (X̅ + X) = AW̅

Subsitutin A from Equation (1), we get:

F = (U̅V + UV̅) W̅

Integrated Circuits (IC):
An IC comprises a number of circuit components like resistors, transistors, etc.
They are interconnected in a single small package to perform the desired electronic function.
These components are formed and connected within a small chip of semiconductor material.

Scale Of Integration:

The number of components fitted into a standard size IC represents its integration scale, it's a density of components.
It is classified as follows:

• SSI (Small Scale Integration):
  It has less than 100 components (about 10 gates).
  Example: MOS chips
   
• MSI (Medium Scale Integration):
  It contains less than 500 components or has more than 10 but less than 100 gates.
  Example: Multiplexers, decoders, counters, and registers.
   
• LSI (Large Scale Integration):
  Here the number of components is between 500 and 300000 or have more than 100 gates.
  Example: Musical instruments, MP3 decoders and telephony receivers, microprocessors.
   
• VLSI (Very Large Scale Integration):
  It contains more than 300000 components per chip.
  Example: Verilog, System Verilog, and VHDL, CPU, ROM, RAM.
   
• VVLSI (Very Very Large Scale Integration): 
  It contains more than 1500000 components per chip.
  Example: Intel 486,  the Pentium series processor.

Concept:

In a 4 × 1 MUX

Truth-Table

Y = Output = S̅1 S̅0 I0 + S̅1 S0 I1 + S1 S̅0 I2 + S1 S0 I3

MUX contains AND gate followed by OR gate

Calculation:

By re-drawing circuit diagram

∴ I0 = 0, I1 = 1, I2 = 1, I3 = 1 & (x = S1, y = S0)

Now output of 4 × 1 MUX is

Y = F = S̅1 S̅0 I0 + S̅1 S0 I1 + S1 S̅0 I2 + S1 S0 I3

F = x̅ y̅ 0 + x̅ y 1 + x y̅ 1 + x y 1

∴ F = x + y