Which of the following statements is INCORRECT for parallel resonance? 

This question was previously asked in
SSC JE Electrical 4 Dec 2023 Official Paper II
View all SSC JE EE Papers >
  1. At resonance, the power factor will be zero. 
  2. At resonance, the impedance will be maximum. 
  3. At resonance, the line current will be in phase with the applied voltage. 
  4. At resonance, the current will be minimum. 

Answer (Detailed Solution Below)

Option 1 : At resonance, the power factor will be zero. 
Free
Electrical Machine for All AE/JE EE Exams Mock Test
7.4 K Users
20 Questions 20 Marks 20 Mins

Detailed Solution

Download Solution PDF

The correct option is 1

Concept:

Parallel resonance, also known as antiresonance, in electric circuits, occurs when the circuit's impedance is at its maximum, causing the current to be at its minimum. At this point, the reactive power is zero because the power factor is unity, indicating zero phase difference between current and voltage.

1) At resonance, the power factor will be zero. - This statement is incorrect. At the point of resonance in a parallel resonance, the circuit is resistive and the power factor is unity, not zero.

2) At resonance, the impedance will be maximum. - This statement is correct. Parallel resonance is defined by the maximum impedance and minimum line current.

3) At resonance, the line current will be in phase with the applied voltage. - This statement is correct. As stated earlier, at resonance, the power factor is unity, meaning the current is in phase with the voltage.

4) At resonance, the current will be minimum. - This statement is correct. At parallel resonance, the circuit impedance is at its maximum, which in turn causes the line current to be at its minimum.

Therefore, among the provided options, the incorrect statement for parallel resonance is:

At resonance, the power factor will be zero.

Latest SSC JE EE Updates

Last updated on May 29, 2025

-> SSC JE Electrical 2025 Notification will be released on June 30 for the post of Junior Engineer Electrical/ Electrical & Mechanical.

-> Applicants can fill out the SSC JE application form 2025 for Electrical Engineering from June 30 to July 21.

-> SSC JE EE 2025 paper 1 exam will be conducted from October 27 to 31. 

-> Candidates with a degree/diploma in engineering are eligible for this post.

-> The selection process includes Paper I and Paper II online exams, followed by document verification.

-> Prepare for the exam using SSC JE EE Previous Year Papers.

Get Free Access Now
Hot Links: teen patti plus teen patti joy mod apk teen patti gold old version teen patti real cash teen patti circle