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Match List I with List II

List I
(Interrupt)

List II
(ROM location (Hex))

(a) Reset

(i) 001B

(b)  External hardware int. 0 (INT0)

(ii) 0003

(c) Timer 0 interrupt (TF0)

(iii) 000B

(d) Timer 1 interrupt (TF1)

(iv) 0000


Choose the correct answer from the options given below:

This question was previously asked in
UGC NET Paper 2: Electronic Science Nov 2020 Official Paper
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  1. (a) - (iv), (b) - (ii), (c) - (iii), (d) - (i)
  2. (a) - (iv), (b) - (iii), (c) - (ii), (d) - (i)
  3. (a) - (iii), (b) - (ii), (c) - (iv), (d) - (i)
  4. (a) - (i), (b) - (ii), (c) - (iii), (d) - (iv)

Answer (Detailed Solution Below)

Option 1 : (a) - (iv), (b) - (ii), (c) - (iii), (d) - (i)
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Detailed Solution

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  • 8051 microcontroller has 5 interrupt signals: INTO, TFO, INT1, TF1, RI/T1.
  • Each interrupt can be enabled or disable by setting bits of the IE register and the whole interrupt system can be disabled by clearing the EA bits of the same register.
  • If INTO, TFO, and INT1 are activated at the same time then they are latched and kept internally.

Explanation:

Interrupt

Flag

Vectored address

Reset

-

0000H

INTO(ext int, 0)

IEO

0003H

Timao

TFO

000BH

INT 1 (ext int.1)

IE1

0013H

Timer 1

TF1

001BH

Serial

TI/RI

0023H


Extra point about 8051 microcontrollers:

  • It is an 8-bit microcontroller
  • It has a 4 kB ROM store, and 40 pins microcontroller (used only 32 pins)
  • Two 8/16 bit timers
  • 64k data memory space.
  • 8051 may also have a special feature like UARTs  ADC, op-amps. etc.
  • Full duplex-serial data transfer.
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