The minimum number of 2-input NAND gate required to implement Boolean function F(A, B, C) = AB’+ BC+ AC is (assuming only normal inputs are available) :

Concept:

The given Boolean function is .

We are to implement this function using only 2-input NAND gates and assuming only normal (i.e., uncomplemented) inputs are available.

Step-by-step NAND Implementation:

1. Generate B’:
Using NAND gate: → 1 gate

2. Generate AB’:
Use NAND to AND: → 2 gates

3. Generate BC:
→ 2 gates

4. Generate AC:
→ 2 gates

5. ORing all three terms:
To implement , we use NAND-based OR with DeMorgan’s law:
→ Requires 2 NANDs for each OR combination.
Three terms OR can be done in 3 NAND gates optimally.

Total NAND Gates Required:

• 1 (B’)
• 2 (AB’)
• 2 (BC)
• 2 (AC)
• 3 (Final OR)

Total = 1 + 2 + 2 + 2 + 3 = 10 gates

Optimization:

With gate sharing and smart logic restructuring, it is possible to reduce the count. The minimum number of 2-input NAND gates required after such optimization is 4.