Question
Download Solution PDFRace Around condition can be avoided in Digital logic circuits using?
Answer (Detailed Solution Below)
Detailed Solution
Download Solution PDFRace around condition in JK flip flop
In JK Flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will toggle as long as CLK is high, which makes the output of the flip-flop unstable or uncertain.
This problem is called race around condition in J-K flip-flop.
The truth table of the JK flip-flop is given below:
|
J |
K |
Qn+1 |
|
0 |
0 |
Qn |
|
0 |
1 |
0 |
|
1 |
0 |
1 |
|
1 |
1 |
Invalid |
The invalid at J=1 and K=1 is known as the race-around condition.
To overcome this condition, a Master-slave JK flip flop is used.
- The master-slave flip flop is constructed by combining two JK flip flops.
- These flip-flops are connected in a series configuration. In these two flip flops, the 1st flip flop work as a "master", called the master flip flop, and the 2nd work as a "slave", called the slave flip flop.
- When the clock pulse is true, the slave flip flop will be in the isolated state, and the system's state may be affected by the J and K inputs.
- The "slave" remains isolated until the CP is 1.
- When the CP is set to 0, the master flip-flop passes the information to the slave flip-flop to obtain the output.
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