In an Op Amp integrator circuit, what is done to, limit the gain at ‘Low Frequencies’?

An ideal Integrator circuit is shown below:

It is clear from the circuit diagram of the integrator, the feedback element is a Capacitor.

Note:

• At high frequencies, the capacitor is a short circuit so the output is 0.
• At zero frequency (0 Hz) or DC, the capacitor acts like an open circuit due to its reactance (1/ωC) thus blocking any output voltage feedback. 
• As a result, very little negative feedback is provided from the output back to the input of the amplifier at low frequencies. 
• Therefore with just capacitor C, in the feedback path, at zero frequency the op-amp is connected like a normal open-loop amplifier with very high open-loop gain (open-loop gain of the op-amp is ideally infinite).
• This high gain can cause op-amp to be unstable and possible voltage rail saturation. 

To avoid undesirable conditions due to high gain. The circuit connects a high-value resistance in parallel with a continuously charging and discharging capacitor C.  The addition of this feedback resistor, R₂ across the capacitor, C gives the circuit the characteristics of an inverting amplifier with finite closed-loop voltage gain given by \(\frac{R_2}{R_1}\)

Therefore, at very low frequencies, the op-amp acts like an inverting amplifier and at very high frequencies the feedback resistor also acts like a short circuit (∵ the impedance of the capacitor is 0) and thus producing output = 0.