Arrange the following logic families in the order of increasing speed: CMOS, low power Schottky TTL, ECL, Schottky TTL, low power TTL, TTL : 

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  1. ECL, Schottky TTL, low power Schottky TTL, TTL, low power TTL and CMOS
  2. TTL, low power TTL, ECL, CMOS, low power Schottky TTL, Schottky TTL.
  3. CMOS, low power TTL, TTL, low power Schottky TTL, Schottky TTL and ECL.
  4. Low power TTL, CMOS, TTL, Schottky TTL, low power Schottky TTL and ECL

Answer (Detailed Solution Below)

Option 3 : CMOS, low power TTL, TTL, low power Schottky TTL, Schottky TTL and ECL.
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Detailed Solution

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The correct answer is option 3.

Comparison between various logic families

Parameter

TTL

RTL

ECL

CMOS

Noise immunity

Very good

Medium

Good

Very good

Propagation delay (ns)

12-6

12

4-1

70

Clock Rate (MHz)

15-60

8

60-400

5

Speed 

Good

Average

Fastest

Slowest

CMOS has the lowest operating frequency, hence its time of operation is highest because time is inversely proportional to the operating frequency.

Since the operating time of CMOS is highest, means its speed is lowest.

Similarly, ECL has the highest operating frequency, therefore its time is lowest and hence operating speed is highest.

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